Senior Firmware Engineer - PCIe/CXL Memory Solutions

United States·San Josesenior

EngineeringEmbedded Engineer

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Quick Summary

Key Responsibilities

Firmware development, bring-up, and validation of PCIe/CXL/DDR interfaces at PHY and Link layers. Interpret technical specifications and develop robust, low-level C code in RTOS environments.

Requirements Summary

Bachelor’s degree in Electrical Engineer

Technical Tools

EngineeringEmbedded Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs is seeking experienced Senior Firmware Engineer PCIe/CXL Memory Solution to lead the design and development of embedded firmware for cutting-edge PCIe/CXL memory expansion products tailored for AI and Cloud infrastructure. This role is pivotal in enabling next-generation memory devices that power high-performance computing platforms. This position will be required onsite.

Bachelor’s degree in Electrical Engineering, Computer Science, or a related technical field.
5+ years of hands-on experience in embedded firmware development using C.
Deep expertise in low-level firmware for hardware bring-up, traffic enablement, and RAS (Reliability, Availability, Serviceability) feature implementation.
Proven track record working with high-speed interfaces and protocols such as PCIe, CXL, DDR, and I2C.
Hands on experience in CPU to Device, Device to Device flows like MMIO, DMA, PCIe P2P.

Responsibilities

~1 min read

→Firmware development, bring-up, and validation of PCIe/CXL/DDR interfaces at PHY and Link layers.
→Interpret technical specifications and develop robust, low-level C code in RTOS environments.
→Collaborate effectively with cross-functional teams and external partners to deliver weekly firmware releases and feature demonstrations.
→Strong debugging skills and ability to triage and resolve issues in complex embedded systems.
→Familiarity with server I/O and memory workflows, performance tuning for latency and bandwidth optimization is a plus.
→Experience with pre-silicon validation in emulation environments is desirable.

The base salary range is 147,000 USD - 165,000 USD for Senior, 175,000 USD - 195,000 USD for Staff, 203,000 USD - 230,000 USD for Principal. Your base salary will be determined based on your relevant experience and the pay of employees in similar positions. This role may be eligible for discretionary bonus, equity, and employee benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.