Senior IC Design Engineer – IO Signal Integrity & Power Delivery

Sunnyvalesenior

Engineering

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Quick Summary

Key Responsibilities

die level, 3d integration, board level Define interface architecture and design specifications, including signaling schemes, impedance targets, and power distribution

Technical Tools

Engineering

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.

Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Senior IC Design Engineer – IO Signal Integrity & Power Delivery

About the Role

~1 min read

10+ years of experience in IC or IO design, analysis, or integration.

Deep understanding of signal integrity, power integrity, and high-speed interface design (DDR, LPDDR, HBM, or similar).

Experience with 3d or 2.5d integration, interposers, die stacking

Strong knowledge of FinFET CMOS technology and transistor-level device behavior.

Expert with HSPICE, FineSim, or equivalent circuit and transient simulation tools.

Experience with channel and package modeling, S-parameter extraction, and time/frequency-domain analysis.

Proficient in IR-drop analysis, PDN optimization, and decoupling network design.

Solid understanding of IO and ESD circuit fundamentals, including protection and clamp strategies.

Experience running aging and reliability simulations and applying results to design optimization.

Strong scripting and automation experience in Tcl, Python, or similar.

Excellent problem-solving, analytical, and cross-functional collaboration skills.

B.S. or M.S. in Electrical Engineering or equivalent required (Ph.D. preferred).

The base salary range for this position is $200,000 to $275,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

What We Offer

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✓Build a breakthrough AI platform beyond the constraints of the GPU.

✓Publish and open source their cutting-edge AI research.

✓Work on one of the fastest AI supercomputers in the world.

✓Enjoy job stability with startup vitality.

✓Our simple, non-corporate work culture that respects individual beliefs.

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

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