Product Engineer, Silicon Validation

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

We are seeking an experienced Product Engineer to lead silicon validation, test program

development, and productization for our large-format AI accelerator chips. In this role, you will develop and execute test strategies from first silicon through high-volume manufacturing, partnering with cross-functional teams and external vendors to ensure production quality and cost targets. This role is critical to achieving first-pass silicon success and seamless NPI-to-HVM transitions.

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  Planning and executing comprehensive silicon characterization from first silicon through production release, including voltage-frequency-temperature characterization, corner testing, guard band determination, and production limit setting

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  Lead test cost optimization efforts while maintaining quality standards

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  Architect test flows to balance test time, coverage, and yield learning objectives for complex AI accelerator designs

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  Drive systematic yield improvement initiatives through data-driven root cause analysis using statistical tools and methods

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  Establish and track key quality metrics including DPPM and test escapes

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  Perform die/package level bring-ups, troubleshoot failure modes, and resolve issues by collaborating with design, system validation, and operations teams

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  Support OSAT bring-up, manage ATE/SLT manufacturing test program releases, and drive toward aggressive test cost goals

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  Productize test programs and methodologies for seamless transition from engineering to high-volume manufacturing

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  Analyze field return data and system-level failures to identify test coverage gaps and implement improved screening methods

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  Drive ATE-system correlation activities to ensure test program accuracy and validate performance against system specs

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  Manage relationships with test vendors, OSAT partners, and foundry partners

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

• 5-10+ years of hands-on experience in silicon validation, product engineering, and ATE test development for advanced node semiconductors

• Proven track record in yield optimization and DPPM reduction with quantifiable results

• Experience with silicon characterization methodologies including Fmax/Vmin characterization and power/thermal validation

• High-volume manufacturing test experience with demonstrated production scale results

• Proficiency in yield and fail pareto analysis using JMP, Exensio, DataPower, or OptimalPlus

• Strong understanding of test program debugging, failure analysis correlation, and yield enhancement techniques

• Experience developing and optimizing ATE test programs for wafer sort and final test on

  Advantest V93K platforms

• Experience managing wafer sort and final test across multiple advanced process nodes

• GPU, HPC, or AI accelerator chip testing background with production scale results

• HBM or high-speed memory interface testing and characterization experience

• Leading NPI through high-volume production with multi-vendor qualification across multiple OSAT sites

• Driving significant cost reduction initiatives

• Multi-site parallel testing strategies and test time optimization for large-format dies

• Scripting and automation skills (Python, Perl, TCL) for test data analysis and workflow automation

• Cross-functional leadership in silicon bring-up and manufacturing ramp

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose and Taipei, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.