~1h ago

Sr. ASIC Layout Design Engineer

United StatesUnited States·Us - Goletasenior
EngineeringDesign Engineer
2 views0 saves0 applied

Quick Summary

Key Responsibilities

Develop high-quality analog/mixed-signal IC layouts and create GDS databases of completed designs using Cadence and Siemens software tools.

Requirements Summary

Bachelor’s degree in engineering or related field with 10+ years of industry experience Expertise in analog/mixed-signal layout design for CMOS circuits, ideally in 180nm, 130nm,

Technical Tools
EngineeringDesign Engineer

Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration and production, medical imaging and pharmaceutical research.​

We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins.

  

  

Responsibilities

~1 min read
  • →Develop high-quality analog/mixed-signal IC layouts and create GDS databases of completed designs using Cadence and Siemens software tools.
  • →Collaborate with circuit designers to optimize floor-planning, placement, and routing.
  • →Ensure layout integrity and compliance to foundry wafer fabrication with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Parasitic Extraction (PEX), and the use of Process Design Kits (PDK).
  • →Interface with ROIC designers, detector engineers, systems engineers, processors, test, and packaging teams to optimize performance, manufacturability and yield.
  • →Present weekly updates to project schedule and percent task completions. Prepare reports for design reviews and internal and external customer presentations.
  • →Perform proper handling of Export Controlled Information and exercise discipline in following GTC protocol and jurisdictional classification.
  • →Release and maintain design documents per the ISO quality system requirements.

  • Bachelor’s degree in engineering or related field with 10+ years of industry experience
  • Expertise in analog/mixed-signal layout design for CMOS circuits, ideally in 180nm, 130nm, or 75nm process nodes
  • Proficiency in Cadence Virtuoso XL for connectivity-aware design
  • Strong understanding of Calibre verification (DRC, LVS) and troubleshooting techniques
  • Experience with custom cell-based layout and top-level floor planning, with work on focal-plane arrays a plus
  • Technical knowledge of wire resistance, coupling capacitance, and best practices for minimizing parasitic effects
  • Excellent communication skills and the ability to work effectively within a multidisciplinary team
  • Programming/scripting skills in SKILL, TCL, Shell, or Python

  

$113,600.00-$151,400.000

The anticipated salary range listed for this role is only an estimate. Actual compensation for successful candidates is carefully determined based on several factors including, but not limited to, location, local regulations (such as minimum wage), education/training, work experience, key skills, and type of position.

Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws, regulations, rules and regulatory orders. Our reputation for honesty, integrity and high ethics is as important to us as our reputation for making innovative sensing solutions.

Teledyne is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age, or any other characteristic or non-merit based factor made unlawful by federal, state, or local laws. ​

Location & Eligibility

Where is the job
Us - Goleta, United States
On-site at the office
Who can apply
US

Listing Details

First seen
September 30, 2026
Last seen
September 30, 2026

Posting Health

Days active
-1
Repost count
0
Trust Level
56%
Scored at
September 30, 2026

Signal breakdown

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Sr. ASIC Layout Design Engineer