Senior Verification Design Automation Engineer

United StatesRemoteFull-timesenior

EngineeringAutomation Engineer

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Quick Summary

Requirements Summary

8+ years of post-college experience in design automation, verification automation, CAD, infrastructure, ASIC verification support, or a closely related field.

Technical Tools

EngineeringAutomation Engineer

This is a remote senior engineering role focused on building and scaling automation infrastructure for advanced ASIC verification environments. You will develop AI-based flows, automation frameworks, and execution environments supporting block, subsystem, and SoC-level verification. The role combines design automation, scripting, infrastructure, and verification expertise to improve engineering productivity and execution efficiency. You will work across simulation, coverage, lint, formal, emulation, and continuous integration workflows. The position offers the opportunity to influence verification practices across geographically distributed engineering teams. You will collaborate closely with verification, design, architecture, and CAD professionals in a highly technical environment focused on high-performance computing and AI networking.

Develop, maintain, and continuously improve AI-based verification flows, infrastructure, automation frameworks, and execution environments used across block, subsystem, and SoC-level ASIC verification.
Build and support scalable regression flows, dashboards, reporting utilities, and triage automation that improve verification productivity, visibility, and issue resolution.
Create and enhance automation scripts, tools, integrations, and workflow utilities using Python, Perl, Tcl, shell scripting, Make, and related technologies.
Support simulation, coverage, lint, formal, emulation, and continuous integration flows while partnering with verification, design, architecture, and CAD teams.
Manage and troubleshoot compute, storage, licensing, queue, and job-dispatch infrastructure issues that affect verification execution and turnaround times.
Drive automation improvements that make verification environments more reliable, reproducible, debuggable, scalable, and efficient across geographically distributed teams.

Requirements

~1 min read

8+ years of post-college experience in design automation, verification automation, CAD, infrastructure, ASIC verification support, or a closely related field.
8+ years of experience developing scripts and automation using Python, Perl, Tcl, shell scripting, or similar programming and automation languages.
Strong experience supporting Linux-based engineering environments, source-control systems, build flows, regression execution, and EDA tool integrations.
Proven ability to debug automation failures, tool and runtime issues, infrastructure bottlenecks, and workflow inefficiencies within complex verification environments.
Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical discipline.
Master’s degree in a related technical discipline is preferred.
Experience with large-scale ASIC verification environments, regression farms, EDA tool flows, and distributed compute infrastructure is preferred.
Knowledge of SystemVerilog and UVM verification methodologies, with the ability to collaborate effectively with verification engineers, is preferred.
Experience with GitHub Actions, Git workflows, job schedulers, data analytics, regression management, coverage tracking, and productivity metrics is a plus.