Senior Package Substrate Design Engineer

Lyte builds perception systems for Physical AI operating in complex environments. The company combines custom silicon, integrated sensors, and software into a unified platform for robotics, mobility, and next-generation automation. Lyte is headquartered in Sunnyvale, California, with a global presence. For more information, visit www.lyte.ai

• We are seeking an experienced Package Substrate Design Engineer to join us and own package and substrate design for the chips and multi-die modules at the heart of Lyte’s fully vertically integrated 4D FMCW LiDAR platform - from early package feasibility and bump/ball planning, through substrate layout and design rule verification, to drawing release and volume production. You will work hands-on with Lyte’s US teams and with our OSAT and substrate supplier partners in Taiwan to deliver manufacturable flip-chip, wire-bond, SiP, and advanced (fan-out / chip-on-wafer) package solutions, along with the test interface hardware that supports them.

• →Own package and substrate physical design for Lyte’s chips and multi-die modules, driving layouts from early planning through implementation, verification, and manufacturing release.
• →Perform package surveys and feasibility studies — body size, bump pad and ball arrangement, die placement, wire length/count estimation, layer count and stack-up options, and routing feasibility — and present cost, performance, and schedule trade-offs.
• →Design package substrates in Cadence Allegro Package Designer (APD) / SiP Layout, including bump maps, escape routing, power/ground distribution, plane design, and controlled-impedance routing for high-speed and sensitive analog/mixed-signal nets.
• →Execute designs across package technologies: flip-chip CSP/BGA (Cu pillar, bump-on-trace), wire-bond FBGA/LGA, stacked-die and side-by-side MCP/SiP, coreless and ETS substrates, and embedded passive (MLCC/IPD) solutions.
• →Extend Lyte’s package design capability to advanced packaging — fan-out RDL (InFO-type), chip-on-wafer and 2.5D/3D integration — including co-packaging of CMOS and silicon photonics die and accommodating optical I/O (fiber attach, optical windows, keep-out zones).
• →Set up design rule constraints from OSAT, foundry, and substrate supplier rule decks; run and resolve DRC/LVS and connectivity checks, working with tool vendors (e.g., Cadence) on complex rule violations.
• →Partner with HQ chip designers on die pad/bump planning and package–die co-design, and with SI/PI, thermal, and mechanical engineers to incorporate simulation results (impedance, crosstalk, IR drop, PDN, warpage, thermal) into the layout.
• →Create and maintain release documentation: substrate unit and strip drawings, bonding diagrams (BD), package outline drawings (POD), stencil and packing tray drawings, Gerber/ODB++ outputs, and design release packages under ECN/change control.
• →Design test interface hardware with Lyte’s test engineers and partner vendors — probe card substrates (multi-DUT MLO/MLC), wafer-level and final-test load boards, and open/short (OS) boards — optimizing layer count, via structures, and DUT layout.
• →Design PCBs for package qualification and failure analysis (e.g., temperature cycling and board-level drop test boards) and support package reliability qualification.
• →Work directly with OSAT and substrate supplier partners on substrate specifications, DFM/DFA reviews, engineering lots, yield issues, and engineering change orders (ECOs).
• →Act as technical project manager for package design workstreams and report status, risks, and production readiness to Lyte’s US-based engineering and Technical Operations leadership.
• →Regularly visit OSATs, substrate suppliers, and test partners in Taiwan and Asia to support NPI and volume production, and provide written reports.

• Bachelor’s degree in Electrical Engineering, Electronic Engineering, Materials Science, Mechanical Engineering, or a related field; advanced degree a plus.
• 8+ years of hands-on IC package and substrate design experience at an OSAT, foundry, fabless/IDM company, or test interface supplier.
• Expert proficiency in Cadence Allegro Package Designer (APD) and/or SiP Layout; working proficiency in Allegro PCB Editor/OrCAD, AutoCAD, and CAM tools (e.g., CAM350).
• Proven design experience on flip-chip (fcCSP/fcBGA) and wire-bond (FBGA/LGA) packages, including bump/ball map planning, stack-up definition, and substrate routing.
• Solid understanding of organic substrate technologies and manufacturing processes (build-up, coreless, ETS, HDI, stacked and through vias) and package assembly processes (flip-chip attach, wire bonding, die attach, molding).
• Experience setting up design rules and resolving DRC/LVS violations against OSAT, foundry, and substrate supplier rule sets.
• Working knowledge of package-level signal integrity and power integrity fundamentals, including impedance control and power/ground distribution.
• Experience producing package release documentation (substrate drawings, bonding diagrams, POD) and manufacturing outputs.
• Experience working directly with OSATs and substrate suppliers on DFM/DFA, engineering builds, and design changes.
• Project management capability/experience is a must, with the ability to manage multiple design projects in parallel and meet schedules.
• Ability to travel within Taiwan and across Asia (up to ~25%) to OSAT, supplier, and partner sites.
• Excellent written and verbal communication skills in English and Mandarin; able to work directly with Lyte’s HQ teams across time zones and with local partners.
• Ability to work independently and take ownership of projects as well as collaborate effectively in a fast-paced, cross-functional startup environment is a must.
• Fast learner with good work ethics is a must.
• Capable of keeping company confidential information and IP is a must.

• Experience with advanced packaging design: fan-out RDL (InFO-type), CoWoS / chip-on-wafer, 2.5D interposers, or 3D-IC, including advanced foundry packaging design rules.
• Experience with package-on-package (PoP/HBPoP) structures, mold through-via / laser via, and embedded passive (MLCC/IPD) substrates.
• Experience designing test interface hardware: vertical probe card substrates (MLO/MLC, multi-DUT), load boards, and open/short boards.
• Hands-on SI/PI, thermal, or warpage simulation (e.g., Ansys SIwave/HFSS, Cadence Sigrity/Clarity, Keysight ADS) is a plus.
• Scripting or design automation skills (e.g., Cadence SKILL, Python) for layout automation and design checks.
• Prior experience at, or working closely with, a Taiwan OSAT, foundry packaging group, or substrate supplier (e.g., ASE/SPIL, Amkor, TSMC advanced packaging, Unimicron, Kinsus, Nan Ya PCB) is highly desired.
• Experience leading design projects or coordinating offshore layout resources is a plus.
• Familiarity with optoelectronic or silicon photonics packaging (fiber attach, optical alignment, laser/photodetector integration).
• Experience with automotive or other high-reliability standards (AEC-Q100/Q104, IATF 16949, JEDEC reliability qualification) is a plus.
• Understanding of silicon photonics, FMCW LiDAR, or related sensing technologies is a plus.

Benefits (subject to location and local regulations)

• Competitive salary and equity 
• Flexible vacation and time-off policy 
• Collaborative, fast-paced, and inclusive work environment 
• Opportunity to work on cutting-edge technologies with a highly cross-functional team