Digital RTL Design Engineer- Static Timing Analysis

Astera Labs is a global leader in purpose-built connectivity solutions for AI and cloud infrastructure. Our semiconductor-based platforms help solve signal, data, and memory connectivity bottlenecks in the world’s most demanding computing systems.

Astera Labs is seeking a Digital RTL Design Engineer- Static Timing Analysis, to join our San Jose design team. In this role, you will contribute to the architecture, implementation, integration, and verification of digital logic for high-performance connectivity and networking ASICs.

You will work with experienced architects and design engineers to translate microarchitectural specifications into robust, synthesizable RTL. You will collaborate closely with verification, physical design, DFT, firmware, systems, and validation teams to deliver reliable designs through synthesis, timing closure, tapeout, and silicon validation.

This is a hands-on opportunity for an engineer who wants to grow expertise in complex ASIC development and contribute to products that enable next-generation AI and cloud infrastructure.

• Develop synthesizable Verilog/SystemVerilog RTL for digital ASIC blocks and subsystems.

• Translate architectural and microarchitectural specifications into datapaths, control logic, state machines, register interfaces, and protocol logic.

• Design reusable and configurable RTL modules for high-performance connectivity products.

• Integrate internal and third-party IP while following established design and coding methodologies.

• Participate in design reviews and contribute to improvements in RTL quality, reuse, performance, power, and area.

• Collaborate with design verification engineers to define functional requirements, test plans, and coverage goals.

• Debug simulation failures using waveform analysis, assertions, regression results, and root-cause analysis.

• Support lint, clock-domain crossing (CDC), reset-domain crossing (RDC), and RTL quality checks.

• Participate in UVM-based verification activities and help resolve functional and integration issues.

• Support gate-level simulation and regression debug as required.

• Support logic synthesis, constraints development, and design implementation flows.

• Perform STA — Static Timing Analysis — and help identify and resolve setup, hold, clock, and interface timing issues.

• Support timing closure, power optimization, and PPA trade-offs in collaboration with synthesis, timing, and physical-design teams.

• Assist with DFT integration, scan requirements, low-power intent, ECOs, and implementation signoff.

• Review reports and debug issues from Cadence and/or Synopsys digital design flows.

• Support block-level and subsystem-level integration through tapeout milestones.

• Collaborate with physical design, DFT, firmware, systems, packaging, and validation teams.

• Participate in silicon bring-up, post-silicon debug, and failure analysis as opportunities arise.

• Document design decisions, issues, and technical solutions clearly for cross-functional stakeholders.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.

• Master’s degree is preferred.

• 3+ years of relevant experience in digital ASIC, SoC, FPGA-to-ASIC, or RTL design, or equivalent academic and industry experience.

• Hands-on experience with Verilog or SystemVerilog RTL development.

• Understanding of digital design fundamentals, including combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces.

• Experience with RTL simulation, debugging, synthesis, and basic timing analysis.

• Familiarity with ASIC design flows and collaboration across design and verification teams.

• Strong communication skills and the ability to work effectively in a collaborative, fast-paced environment.

• Ability and willingness to work onsite in San Jose, California.

• Experience with PCI Express, Ethernet, NVMe, CXL, UALink, AMBA, or other high-speed communication and interface protocols.

• Experience with networking controllers, packet-processing logic, storage controllers, interconnects, NoCs, DPUs, SmartNICs, or data-center ASICs.

• Familiarity with synthesis and implementation tools such as Cadence Genus/Innovus or Synopsys Design Compiler/ICC2.

• Experience with STA — Static Timing Analysis — using tools such as Synopsys PrimeTime or Cadence Tempus.

• Familiarity with lint, CDC/RDC, DFT, scan, GLS, LEC, UPF, or formal-verification flows.

• Experience with UVM, SystemVerilog Assertions, functional coverage, or verification-plan development.

• Experience with Python, Tcl, Perl, Shell, or other scripting languages for design and verification automation.

• Exposure to advanced-node CMOS design, tapeout, silicon bring-up, or post-silicon validation.

• Experience working with physical-design teams on floorplanning, congestion, timing, power, and implementation challenges.