Physical Design CAD Lead

Israellead

EngineeringOtherDesign LeadPhysical Design Cad

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Overview

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners,

Technical Tools

EngineeringOtherDesign LeadPhysical Design Cad

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design CAD Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design CAD Lead, you will be responsible for the physical implementation environment. Your primary mission is to build, optimize, and support the automated flows from RTL to manufacturable GDSII tape-out. You will own the flows, Database and will support the whole PD team to optimize their blocks for Power, Performance, Timing while keep the team aligned on Methodical, Efficient and balanced work Environment.

Responsibilities

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→Design and maintain automated flows for Synthesis, Place & Route, and Floor-planning
→Develop robust environments for Static Timing Analysis, Power Analysis, and Physical Verification (DRC/LVS/ERC)
→Write custom plug-ins and scripts to extend the capabilities of vendor tools, tailoring them to our specific process node constraints and flows
→Create automated "dashboards" and feedback loops to help design teams track and improve Power, Performance, and Area metrics across iterations
→Collaborate with EDA vendors (Synopsys, Cadence, Siemens/Mentor) as consulters for our developed flows and results analysis

Requirements

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B.Sc in Electrical Engineering
Professional experience with back-end industrial tool suites (e.g., Synopsys Fusion Compiler or Cadence Genus, Innovus)
Expert-level proficiency in Tcl and Python for high-level flow automation and data parsing
Deep understanding of Physical Design concepts including clock tree synthesis, routing congestion, timing closure, and signal integrity
Hands-on experience with sign-off flows
Very good communication skills

Nice to Have

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Experience with 5nm, 3nm and more advanced processes
Knowledge of compute farm management (LSF/Slurm) and revision control (Git) for managing massive design databases

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.