Enphase Energy is a global energy technology company and a leading provider of solar, battery, and electric vehicle charging products. Founded in 2006, our innovative microinverter technology revolutionized solar power, making it a safer, more reliable, and scalable energy source. Today, the Enphase Energy System enables users to make, use, save, and sell their own power. Enphase is also one of the most successful and innovative clean energy companies in the world, with more than 80 million products shipped across 160 countries.

Join our dynamic teams designing and developing next-gen energy technologies and help drive a sustainable future!

This role at Enphase requires working onsite 3 days a week, with plans to transition back to a full 5 day in office schedule over time.

About the role

Enphase is looking for mid-level engineer to join our team in Bangalore India with verification experience in System Verilog for RISC-V based subsystem to be used in our ARM Cortex M4 based ASICs. The team is working on development of our next generation Control ASIC to production in 22nm technology. The ASIC will be a Mixed Signal SOC built around ARM microcontrollers.

What you will be doing

Work on creating verification plan for RISC-V based application specific IP
Build Standalone IP test bench using System Verilog
Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC)
Use the IP/SOC RTL in system Verilog based logic verification environment & complete the functional verification
Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality
Deliver the functional test vectors needed to be used for post-silicon validation
Be the single point contact for the concerned IP Verification and enable the Tapeout for all control ASICs of Enphase

Who you are and What you bring

Proficient in UVM, Verilog, System Verilog, C, Python. Working on the HW/SW interface
Strong understanding and experience of logic verification environment (UVM & System Verilog)
Strong understanding of RISC-V architecture & functional verification
Experience with processor toolchains (compiler, assembler, simulator)
Experience with processor verification. Directed tests and random program generated tests
Experience with functional processor simulators
Experience with verification of secure processor boot code
Experience with Floating point instructions implementation & verification in micro controller-based ASIC designs
Ability to quickly adapt to other categories of C-based/System Verilog based IP verification
Experience and ability to bring complex SOCs into the physical world and into production
Excellent problem-solving skills, written & verbal communication skills
#Logic Verification #Embedded C Verification #ARM #Boot
Prior hands-on work experience of at least 8 years in Logic IP Verification based on System Verilog

Senior Staff Verification Engineer

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