FPGA Design Engineer (m/f/d)

Key responsibilities:

• Define FPGA architecture for:
  • Real‑time communication and control loops.
  • Power electronics–specific functions (PWM, gating, protection, measurements).
  • Partition functions between FPGA, MCU/DSP, and other devices considering latency and determinism.
  • Select appropriate FPGA families and IP for timing‑critical and safety‑related functions.
• Develop synthesizable RTL (VHDL) for:
  • PWM generators (e.g., carrier‑based, space‑vector, multi‑phase, interleaved, dead‑time insertion, synchronised to grid or rotating frame).
  • Real‑time communication interfaces (e.g., synchronous serial links, fieldbus/industrial Ethernet PHY interfaces, deterministic point‑to‑point links, custom high‑speed serial).
  • Signal and clock reconstruction blocks (e.g., digital PLLs, phase tracking, clock domain crossing, resampling, and timestamping).
  • Measurement, protection, and monitoring logic (e.g., overcurrent, overvoltage, desaturation, fault latching, fast trips).
• Implement:
  • High‑resolution timers and counters for gating signals.
  • Clock, reset, and synchronization schemes for multi‑board/multi‑FPGA systems.
  • Fixed‑point digital signal processing as needed for filtering, estimation, or modulation.
• Develop testbenches and simulations to verify:
  • PWM timing accuracy, dead‑time behavior, and jitter performance.
  • Real‑time communications latency, robustness, and error handling.
  • Correct operation of signal/clock reconstruction (phase tracking, frequency changes, grid disturbances).
• Perform static timing analysis and timing closure for:
  • Tight real‑time constraints (fast control loops, sub‑µs reaction times).
  • Multiple clock domains and asynchronous interfaces.
• Support lab and field testing:
  • Board bring‑up and system integration.
  • Debugging under real operating conditions using oscilloscopes, logic analyzers, current/voltage probes, and protocol analyzers.
• Create and maintain documentation:
  • FPGA specifications, timing budgets, and interface definitions.
  • Verification plans, test reports, and release notes.
• Support production and field updates (JTAG, in‑system programming, secure and fail‑safe update mechanisms).

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Your Profile:

• Bachelor’s or Master’s degree in Electrical Engineering, Information Technology, Computer Engineering, or a related field, with a focus on FPGA or digital hardware design.
• Several years of professional experience in FPGA design, preferably in real-time, control, or power electronics applications.
• Strong proficiency in VHDL and a solid understanding of synthesizable RTL design, timing constraints, and clock domain crossing techniques.
• Hands-on experience with at least one major FPGA vendor toolchain.
• Experience with time-critical logic such as PWM generation, high-resolution timers, or communication interfaces.
• Fluency in English is required; German is a plus.

Key Competencies:

• Strong problem‑ solving skills in time‑critical and safety‑related systems.
• High attention to detail, especially regarding timing, jitter, and protection logic.
• Ability to collaborate with control, power electronics, hardware, and firmware teams.
• Clear communication of complex timing and architecture decisions.

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We offer:

• Company bound by a collective bargaining agreement with 35 hours/week and 30 days of vacation

• Flexible working time arrangements

• On-site canteen in Berlin

• Welcome Days for the perfect start in a global company