~5h ago
New

Senior FPGA Design Engineer

Us-In-Ft Wayne-150a ~ 1010 Production Rd ~ Bldg 150asenior
OtherFpga Design Engineer
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Quick Summary

Key Responsibilities

AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus Prime Pro or Libero. Generate FPGA designs for the following applications: gigabit serial interfaces,

Requirements Summary

The ability to obtain and maintain a U.S. government issued security clearance is required.​ U.S. citizenship is required, as only U.S.

Technical Tools
OtherFpga Design Engineer
2026-06-24
United States of America
US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A
Onsite

Requirements

~2 min read
The ability to obtain and maintain a U.S. government issued security clearance is required.​ U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance
  • Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 5 years of prior relevant experience.

  • Experience to include one or more of the following:

    • FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)

    • Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.

    • Hands on experience with integration and debug of FPGA/ASIC in a lab environment

    • Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.

    • Experience with source code management, design reviews, and code release in a team development environment.

  • One or more advanced degrees in Electrical Engineering or a related Science, Technology, Engineering, or Mathematics (STEM) major.  A suitable degree may be counted as 2 years of work experience."

  • FPGA/ASIC design experience in one or more of the following areas:

    • Radar processing techniques

    • Image processing techniques for visual and infrared sensors

    • Embedded systems design using ARM, Microblaze, or NIOS processors

    • Gigabit serial interfaces and multi-gigabit transceivers (MGTs)

    • Constrained random verification in UVM using System Verilog

    • Experience with High Level Synthesis (HLS)

    • Experience with vector processors and/or GPUs

  • Demonstrated ability to lead teams to achieve schedule, budget and technical commitments. 

  • Experience with project management tools such as Earned Value and/or Agile Execution.

  • Proposal development experience.

DoD Clearance: Secret
Active and existing security clearance required after day 1

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.

The Multi-Product Power & Digital (MPD) department designs FPGAs, circuit cards, and electronics subassemblies for a range of products including missiles/effectors, radars, and electronic warfare systems.  The team leverages digital, analog, and power design skills to provide support throughout the product lifecycle from architecture and design through production and sustainment.

The MPD department is seeking a Senior FPGA Design Engineer to join our team. In this role, you will leverage advanced technologies to create cutting-edge solutions for sensor and effector products. You will partner with experienced, multidisciplinary teams to define requirements, develop architectures, execute detailed design and simulations, and perform integration and verification tasks. You will document your designs within the appropriate configuration management tools and provide comprehensive engineering support throughout the product lifecycle.

Responsibilities

~1 min read
  • →

    Provide full lifecycle support of production quality FPGA designs for all major vendors and device families including: AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus Prime Pro or Libero. 

  • →

    Generate FPGA designs for the following applications: gigabit serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.

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    Support translation of system level requirements into FPGA requirements

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    Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)

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    Lead FPGA designs and code in VHDL for reliability and maintainability

  • →

    Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage

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    Define schedules for FPGA tasking and drive execution to the planned budget and schedule.

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    Create complete documentation including requirements, verification plan, and user’s guides

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    Lead individual designs and/or small teams.

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    Operate with minimal oversight from manager.

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    Support internal and external technical reviews.

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    Engage in knowledge transfer activities and mentorship of junior engineers.

Click on this link to read the Policy and Terms

What We Offer

~1 min read

Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value: Trust, Respect, Accountability, Collaboration, and Innovation.

This position offers relocation based on candidate eligibility.

This position requires a security clearance. DCSA Consolidated Adjudication Services (DCSA CAS), an agency of the Department of Defense, handles and adjudicates the security clearance process. More information about Security Clearances can be found on the US Department of State government website here: https://www.state.gov/m/ds/clearances/c10978.htm

Location & Eligibility

Where is the job
Us-In-Ft Wayne-150a ~ 1010 Production Rd ~ Bldg 150a
On-site at the office
Who can apply
Same as job location

Listing Details

First seen
October 1, 2026
Last seen
October 1, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
56%
Scored at
October 1, 2026

Signal breakdown

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Senior FPGA Design Engineer