R&D FPGA Developer in HVDC MACH

Our R&D engineers and scientists develop breakthrough technologies that change the way the world works, and industries do business. We constantly push the limits of convention, while retaining our focus on delivering quality products and solutions to our customers.

Over 60 years ago, Hitachi Energy introduced a new way of transmitting electricity across long distances with minimum losses – High Voltage Direct Current (HVDC). HVDC technology can now deliver up to 12 gigawatts of power at voltage levels of up to 1,100 kV, covering distances of more than 3,000 kilometers. 

You will contribute significantly to successful results in the heart of HVDC station: Modular Advanced Control for HVDC (MACH™). The MACH™ control system provides unequalled calculation capacity and enables a high degree of integration and handling for all control and protection functions. Moreover, MACH™ control provides advanced fault registration and remote control functions. The system is designed to run 24/7 for thirty years or more, allowing the HVDC system to be controlled and protected in the most reliable way throughout its life time.

As a part of global R&D organization you will cooperate on daily bases with colleagues from MACH teams in Sweden and India. Development in Krakow covers DSP Control & Protection, I/O systems, Power Electronics units and robust communication. FPGA development is done on chips delivered by Xilinx, Lattice and Microsemi. You are going to work in the team led by Maciej Mech.

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  Participation in the full development lifecycle of FPGA-based devices, from requirements analysis and architecture definition through implementation, integration, validation, and deployment.

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  Design, implementation, simulation, debugging, and maintenance of FPGA solutions using VHDL and modern AMD/Xilinx FPGA platforms.

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  Investigation and evaluation of alternative technical approaches, supporting architectural decisions through feasibility studies, proof-of-concept development, and technical risk reduction activities.

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  Development of reusable verification and validation infrastructure.

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  Collaboration with hardware, architecture, and software teams to define interfaces, resolve cross-domain technical issues, and ensure successful system integration.

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  Analysis and clarification of system requirements, translating high-level functional expectations into implementable FPGA and system-level solutions.

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  Creation and maintenance of technical documentation, including interface specifications, design diagrams, test plans, and engineering guidelines. 

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  Support of prototype bring-up, laboratory testing, and hardware validation activities on real target platforms.

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  Contributing to knowledge sharing across engineering teams through technical reviews, design discussions, engineering presentations, and documentation of lessons learned.

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  Participation in cross-functional planning, technical coordination, and engineering decision-making activities throughout the product development process.

• At least 2 years of experience of FPGA/ASIC design & simulation in VHDL (or Verilog).

• Good understanding of synchronous design, time constraining and static timing analysis.

• Experience in modelling in High Level Synthesis.

• Knowledge of GIT, CI/CD principles and Azure Devops pipelines.

• Experience in self-testing test-benches and regression tests.

• Experience with laboratory equipment, prototyping and testing.

• Strong commitment to safe work practices and dedication to follow all relevant workplace safety guidelines.

• High level of self-motivation, curiosity, and desire to learn about modern technologies.

• A collaborative, solutions-oriented approach, and effective communication skills.

At Hitachi Energy, we recognize that our people are at the heart of our success. We are committed to providing a supportive and inclusive workplace, competitive rewards, and opportunities for professional and personal growth. Our benefits package is designed to help employees thrive both at work and in their personal lives.