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Staff Engineer Digital Functional Verification (f/m/div)

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#WeAreIn for jobs that impact everyone's life. What if your ideas could change the way the world connects, powers up,

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#WeAreIn for jobs that impact everyone's life. What if your ideas could change the way the world connects, powers up, or thinks? As a Staff Engineer Digital Functional Verification in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.  Are you in? Your role Key responsibilities in your new role As a Staff Engineer Digital Functional Verification, you will develop UVM-based verification environments, implement test scenarios using System Verilog, and ensure low-power verification using UPF. By applying Formal Verification, driving knowledge exchange, and collaborating with global and cross-disciplinary teams, you will contribute to the development of innovative and high-quality products. Be in continuous and intensive contact  with our  development sites worldwid e and support the experts from our business units in verification projects Contribute actively  to the  internal exchange  of know-how and experience at Infineon Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan Design and develop the verification environment  for ICs using the "Universal Verification Methodology" (UVM) Identify sub-modules that are particularly suitable for specific verification method  (Simulation based / Formal Verification) and apply selected methodology Implement test scenarios using System Verilog and verify functionality using a Constrained Random Approach Define and control verification management activities on module level, such as verification planning, verification tracking and reporting Your profile Qualifications and skills to help you succeed  You are a detail-oriented and solution-driven professional with strong problem-solving skills and a commitment to high-quality outcomes. With excellent communication abilities, you thrive in dynamic, cross-functional teams, fostering collaboration and driving continuous improvement. A degree in Electrical Engineering, Computer Science or a similar academic discipline At least 5 years of professional experience in Metric Driven Verification  (digital & mixed signal) and Formal Verification Experience in the creation and dissemination of methods in functional verification  (SystemVerilog) An excellent understanding of SystemVerilog/UVM along with strong practical skills in their application (PA/UPF as a plus) Knowledge of RTL design (SystemVerilog/VHDL ) as well as SVAs, PSL, Formal Verification and mixed-signal verification  is a plus Experience with  Ethernet protocols  (bridge, PHY, MACs),  Cadence verification software,  and  technical leadership  or project management is considered a plus Fluency in English  (mandatory) Please send us your CV in English. #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.  Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon. Diana Sabença, LinkedIn

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Posted
October 12, 2026
First seen
October 12, 2026
Last seen
October 12, 2026

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October 12, 2026

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Staff Engineer Digital Functional Verification (f/m/div)