Senior Analog/RF Layout Engineer

As a Senior Analog/RF Layout Engineer, you will contribute to all phases of physical design—from concept through tapeout—focused on block-level layout with support for top-level integration. Working with circuit designers, packaging, process, and product teams, you will build robust, manufacturable layouts that meet performance, reliability, area, and schedule goals, helping deliver high-speed electrical IP such as SerDes, PAM4 interfaces, D2D PHY, and clocking subsystems.

• →Drive layout and physical implementation of analog/mixed-signal circuits, high-speed interfaces (SerDes, PAM4), and supporting digital blocks.
• →Own block-level floorplanning, placement, routing, and integration for complex mixed-signal ICs.
• →Translate schematics and performance targets into optimized layouts—tuned for matching, parasitics, signal/power integrity, thermal behavior, yield, and manufacturability.
• →Ensure compliance with all foundry rules (DRC, LVS, ERC, density, EM/IR, reliability).
• →Support top-level assembly across analog, digital, and high-speed domains (SerDes, PAM4 paths, clocking, control logic).
• →Review post-layout extraction and support simulation closure, applying best practices for symmetry, shielding, and isolation.
• →Partner with packaging and product teams on bump planning, pad ring, ESD structures, and package integration.
• →Drive layout-related issues affecting performance, yield, or production readiness; contribute to reviews on feasibility, tradeoffs, and tapeout risk.
• →Support tapeout readiness (database checks, signoff), CAD flow/automation improvements, mentoring of junior engineers, and post-silicon debug of layout issues.

Strong hands-on command of the Cadence Virtuoso custom-design platform is essential—deep tool fluency keeps the learning curve short. We expect working expertise across the following (or close equivalents):

• Virtuoso Layout Suite (XL / GXL) for connectivity- and constraint-driven custom layout, including Modgen and structured/array generation for matched devices.
• EM simulators like EMX, HFSS, Lorentz Peakview, etc.
• Virtuoso Electrically Aware Design (EAD) for in-design EM/IR and parasitic-aware high-speed layout.
• Quantus QRC extraction; physical verification with Cadence Pegasus (or Assura) and/or Siemens Calibre — DRC, LVS, ERC, density.
• Voltus-Fi / Virtuoso Power for EM/IR signoff; SKILL scripting plus Python / Perl / TCL for automation.

• Bachelor's in Electrical Engineering or related (Master's a plus), with 6–8 years in custom IC layout for analog, mixed-signal, and high-speed designs.
• Strong foundation in matching, symmetry, shielding, parasitic control, thermal management, and signal integrity, with interest in growing into layout leadership.
• Command of device-level techniques (common-centroid, interdigitation, guard rings, isolation structures).
• Solid grasp of DRC, LVS, ERC, parasitic extraction, EM/IR analysis, and physical signoff flows; comfortable working in Linux.
• Familiarity with ASIC/SoC tapeout processes and layout automation scripting is preferred.
• Strong analytical, problem-solving, communication, and teamwork skills, effective across geographically distributed teams.

• Bachelor's or Master's in Electrical Engineering or equivalent field.
• 3+ years of layout design experience in analog, mixed-signal, or high-speed IC development.
• Hands-on experience taking block-level layout through tapeout.
• Strong custom-layout, physical-verification, and parasitic-aware implementation skills with Cadence Virtuoso or comparable tools.