From $35/yr

TOP Design Verification Engineer Intern

United StatesUnited States·San Joseentry
OtherDesign Verification Engineer
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Quick Summary

Requirements Summary

A Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) or a related field is required. Digital IC Design & Verification experiences. Work in Windows and Linux environment.

Technical Tools
OtherDesign Verification Engineer

 

Responsibilities

~1 min read
  • A Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) or a related field is required.
  • Digital IC Design & Verification experiences.
  • Work in Windows and Linux environment.
  • Python or Perl scripting experience.
  • Experience in System Verilog, UVM, C/Assembly coding
  • Experience in Perforce and Confluence.
  • Familiarity with UCIe, CPU architecture, NAND protocols, and AI productivity tools is a plus.

 

What We Offer

~1 min read

 

Location & Eligibility

Where is the job
San Jose, United States
On-site at the office
Who can apply
US

Listing Details

Posted
September 3, 2026
First seen
September 4, 2026
Last seen
September 4, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
60%
Scored at
September 4, 2026

Signal breakdown

freshnesssource trustcontent trustemployer trust
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TOP Design Verification Engineer InternFrom $0k