Hardware Engineer (FPGA)
Quick Summary
Virtu is a leading financial firm that leverages cutting edge technology to deliver liquidity to the global markets and innovative, transparent trading solutions to our clients. As a market maker,
Virtu is a leading financial firm that leverages cutting edge technology to deliver liquidity to the global markets and innovative, transparent trading solutions to our clients. As a market maker, Virtu provides deep liquidity that helps to create more efficient markets around the world. Our market structure expertise, broad diversification, and execution technology enables us to provide competitive bids and offers in over 19,000 securities, at over 235 venues, in 36 countries worldwide.
Virtu's Hardware Design team builds the FPGA and ASIC applications at the core of the firm's proprietary low-latency trading platform.
We are looking for an FPGA/ASIC Engineer to join us. The ideal candidate will be a creative and ambitious hardware engineer who is excited to work on our low-latency trading infrastructure. You'll work on challenging problems alongside a small, international team.
In this role you will:
- Design and develop RTL for new low-latency trading applications
- Own designs end to end, from specification through verification to production deployment
- Improve the team's build, simulation, and verification infrastructure
- Coordinate and execute hardware deployments in live production environments
Virtu offers a dynamic, meritocratic environment with a flat hierarchy. No finance background is necessary or expected. This is a great opportunity for the right candidate to start a career in the financial technology space.
- Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or a related field
- 2+ years of professional FPGA or ASIC experience (an advanced degree may substitute)
- Strong RTL design and verification skills (SystemVerilog/VHDL, cocotb)
- Familiarity with FPGA/IC design flows and vendor toolchains (Xilinx/AMD, Synopsys, Cadence)
- Working knowledge of high-speed interfaces (Ethernet/MAC/PHY, PCIe, AXI)
- Programming in Python, C++, or similar
- Back-end physical design experience
- Understanding of network protocols and packet processing (TCP/UDP, IP multicast, and hardware protocol offloading)
What We Offer
~1 min readLocation & Eligibility
Listing Details
- Posted
- September 4, 2026
- First seen
- September 5, 2026
- Last seen
- September 5, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 67%
- Scored at
- September 5, 2026
Signal breakdown
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