Design Verification Engineer - Analog Mixed-Signal (AMS) | BCP

The Battery Charging Products group at Texas Instruments is looking for a candidate that is interested in working in a challenging, fast-paced environment.  As a Design Verification Engineer-AMS you will get to directly interact with one of TI's high-volume and high-impact customers and will help architect new TI battery charger products and make our customers’ visions a reality. You will define, design, model, and document digital cores for battery management devices.   We are looking for a self-motivated, highly driven AMS Verification Engineer to make an immediate impact on current developments, and help us grow market share in a competitive, constantly changing market.

TI offers an extraordinary culture, competitive benefits, professional development opportunities and collaboration coupled with a social responsibility. A career at TI provides the chance to work with some of the world's most dynamic technologies that help people learn, grow, connect and discover.

• Verification Strategy: Develop detailed coverage-driven Verification Plans by collaborating closely with System, Application, and Analog Design teams.
• Modelling & Simulation: Create high-fidelity Analog behavioral models using Verilog-A, Verilog-AMS, Wreal (RNM), to enable efficient top-level simulation.
• Environment Development: Build and enhance mixed signal testbenches using a combination of schematic, models, and RTL.
• Checkers & Assertions: Implement real-time analog checkers and post-processing checker strategies to ensure functional correctness.
• Full-Cycle Verification: Execute RTL and Gate Level Simulations (GLS), running regressions and tracking functional coverage goals until tape-out.
• Collaboration: Work with Digital DV Team, Analog Designers, and Post-Silicon Validation teams to debug complex issues and ensure successful product delivery.

• Education: Bachelor’s or master’s degree in electrical engineering (EE) or Electronics and Communication Engineering (ECE) 
• Experience: Minimum 3 years of hands-on experience in Analog Mixed-Signal (AMS) design verification.  
• Modelling Skills: Proficiency in analog behavioral modelling using System Verilog, Verilog-AMS, Verilog-A, or Wreal.  
• Verification Flow: Direct experience with mixed-signal verification involving a combination of schematic, behavioral models, and RTL.  
• Tool: Strong command of Cadence Virtuoso/AMS Designer toolsets and debug environments or other standard mixed-signal simulation tools
• Communication: Clear ability to present technical analysis and conclusions to internal stakeholders and business leaders.  
• Excellent self-organizing and time management skills.

• Advanced DV: Knowledge of UVM, as the top-level environments are built on these frameworks.  
• Automation: Proficiency in scripting (Python, Perl, or Shell) to automate simulation flows and data analysis. Exposure and interest in building AI-driven verification methodologies. 
• Domain Expertise: Experience in signal processing, PMICs, or high-speed communication interfaces.  
• Silicon Interaction: Experience in silicon debug and working alongside silicon validation teams. 
• Standard protocols exposure: Verification experience with I2C, SPI, UART etc.