Senior Packaging Engineer

Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors.

Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs.

Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles:

1. Do great things: we deliver work we’re proud to sign our name to.

2. High velocity: speed matters. We move quickly, one step at a time.

3. One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie.

Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders.

As a Senior Packaging Engineer, you will lead IC packaging initiatives from conceptualization and design to manufacturing process selection. You will establish the necessary supply chain, manage sub-contractors, and oversee the NPI and ramp-up phases for current and future Arago devices.

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  Design packaging solutions spanning from initial drawings and simulations to DFM.

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  Identify, vet, and manage external sub-contractors.

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  Collaborate cross-functionally with IC design, optical, and PCB teams to align packaging specifications across domains.

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  Lead the chip industrialization process, ensuring high yield and Cpk.

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  Conduct thorough failure analysis and debugging.

• Master's degree in Electrical Engineering or Integrated Circuits Design.

• 5+ years of experience in the semiconductor and photonic packaging industry.

• Proficiency in heterogeneous integration and packaging processes, including wafer dicing (stealth, blade, diamond scribing), high-density Cu pillars and advanced bumping, flip-chip, redistribution layer and encapsulation (thermal lid, compression molding, glob-top), die attach and bonding techniques (epoxy, attach film, reflow, thermocompression, eutectic, laser-assisted bonding, Cu-Cu direct bonding), wirebonding, and 2.5D/3D integration schemes (back grinding, TSV reveal, die stacking, interposer).

• Strong expertise in photonic and optoelectronic packaging and micro-scale optical alignment, including passive and active alignment of lenses and optical fibers, fine die placement (precision < 1µm), and experience with InP, GaAs, and other non-Si semiconductors.

• Proficiency in thermal, mechanical, and EM simulations.

• Experience with Cadence Allegro Package Designer, Altium, Cadence Virtuoso, Cadence Sigrity, ANSYS Mechanical, HFSS, and SIwave.

• Strong understanding of packaging industrialization, production flows, high-yield and scale manufacturing, failure analysis, and Six Sigma methodology is a plus.

• Language: English at a proficient level. French is a plus.