Senior/ Staff Physical Design CAD Engineer - Automation & Signoff

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.

• →Develop and maintain automated flows for Synthesis, Place & Route (P&R), and Floor-planning to ensure seamless design transitions
• →Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)
• →Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints
• →Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations
• →Own the design database structure and version control to ensure team alignment and data integrity
• →Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results
• →Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing

• Bachelor’s degree in Electrical Engineering or a related technical field
• 5+ years of hands-on professional experience with back-end industrial tool suites (e.g., Synopsys Fusion Compiler or Cadence Genus/Innovus)
• Expert-level proficiency in Tcl and Python for high-level flow automation, data parsing, and tool customization
• Deep technical understanding of Physical Design concepts, including clock tree synthesis (CTS), routing congestion, timing closure, and signal integrity
• Proven experience executing sign-off flows for complex, high-performance designs
• Strong communication skills and a collaborative approach to solving complex engineering bottlenecks

• Hands-on experience with 5nm, 3nm, or more advanced process nodes
• Practical knowledge of compute farm management (LSF/Slurm) and revision control (Git) for managing massive design databases
• Experience in developing proprietary automation wrappers for industry-standard EDA tools