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Asteralabs15h ago

Senior/Tech Lead Silicon Validation Engineer

United StatesSan Josesenior
EngineeringManagementSenior
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Quick Summary

Requirements Summary

At Astera Labs,

Technical Tools
EngineeringManagementSenior

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Requirements

~1 min read
  • Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
  • ≥3 years’ experience testing, supporting or developing complex SoC/silicon products and high-speed IO/SerDes electrical interface for Server, Storage, and/or Networking applications.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
  • Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
  • Proven track record solving problems independently, preferably as a tech lead.
  • Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3x Ethernet.
  • Strong problem-solving skills, ability to solve problems independently.
  • Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, and both NRZ and PAM4 signaling.
  • Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration.
  • Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Nice to Have

~1 min read
  • Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels
  • Familiarity with PCIe or Ethernet especially Electrical Compliance sections
  • Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces
  •  Working knowledge of C or C++ for embedded FW
  •  Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling
  •  Working knowledge of common serial data specifications such as I2C, SPI, etc
  •  Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $148,500 USD - $165,000 USD for Senior level, and $175,000 USD - $195,000 USD for Staff level.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Listing Details

Posted
April 14, 2026
First seen
March 26, 2026
Last seen
April 15, 2026

Posting Health

Days active
19
Repost count
0
Trust Level
68%
Scored at
April 15, 2026

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Senior/Tech Lead Silicon Validation Engineer