RTL Design and Verification Consultant – Part Time Remote

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OtherRtl Design Engineer

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Quick Summary

Overview

RTL Design and Verification Consultant – Part Time Remote Location: Remote, Nationwide Join an innovative and fast-growing technology organization at the forefront of advancing intelligent systems through cutting-edge digital hardware expertise.

Key Responsibilities

Develop complex RTL design challenges that reflect real-world hardware scenarios Create high-quality Verilog or SystemVerilog solutions for digital design problems Design and implement robust testbenches to validate functionality and performance…

Requirements Summary

Master’s or PhD in Electrical Engineering, Computer Engineering, or related discipline Deep knowledge of RTL design or verification Strong proficiency in Verilog or SystemVerilog Understanding of simulation, debugging, and waveform analysis tools…

Technical Tools

python

Responsibilities

~1 min read

→Develop complex RTL design challenges that reflect real-world hardware scenarios
→Create high-quality Verilog or SystemVerilog solutions for digital design problems
→Design and implement robust testbenches to validate functionality and performance
→Evaluate generated RTL outputs for logical accuracy, timing integrity, and design efficiency
→Build and enhance automated evaluation workflows using simulation and scripting tools
→Introduce edge cases and stress scenarios to strengthen system robustness and reliability
→Collaborate with cross-functional teams to refine validation methodologies and improve outcomes

Digital RTL design and finite state machine development
Verification strategies, including testbench architecture and simulation analysis
Clock domain crossing techniques and timing considerations
Debugging workflows and waveform interpretation

Requirements

~1 min read

Master’s or PhD in Electrical Engineering, Computer Engineering, or related discipline
Deep knowledge of RTL design or verification
Strong proficiency in Verilog or SystemVerilog
Understanding of simulation, debugging, and waveform analysis tools
Scripting experience, preferably with Python, for automation tasks

Requirements

~1 min read

Exposure to ASIC or FPGA development flows
Understanding of static timing analysis principles
Familiarity with open-source or commercial simulation tools

Verilator, Icarus Verilog, Yosys, cocotb, GTKWave, or comparable environments

Flexible, part-time remote engagement
Work on highly impactful projects at the intersection of AI and hardware design
Collaborate with forward-thinking technical teams solving complex challenges
Opportunity to influence emerging methodologies in automated design validation

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