ASIC Design Engineer

At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.  

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.  

Cornelis Networks is hiring talented ASIC Design Engineers with deep experience in one or more of the key areas required to build the world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions.

Key Responsibilities

• Implementation of the advanced ethernet protocols for the next generation ethernet ASICs.  
  

• Write micro architecture specifications. 
  

• Pre-silicon: Define timing constraints for the RTL block and work with Physical Design engineers for timing optimization.
  

• Pre-silicon: Work with the verification engineers to create block/system level test plans and ensure that the design is adequately covered.
  

• Post-silicon: Work with hardware/firmware/software engineers to resolve ASIC issues.  
  

Minimum Qualifications

• B.S. or M.S.  degree in Computer or Electrical Engineering. 
  

• 3 + years of post-college experience in digital design with proficiency in Verilog, System Verilog.
  

• Relevant experience in timing closure and familiarity with modern physical design methodologies.
  

• Demonstrated strength with system level debug and determining root cause of technical issues.
  

• Strong verbal and written communications skills.

Preferred Qualifications

• Experience with Ethernet architecture and Networking protocols. 
  
• Familiarity and experience in design of some ethernet protocols applicable to ethernet adapters and switches.
  
• Experience with multiple clock designs and asynchronous interfaces

Job Location: This role may work remote from Costa Rica via an EOR (Employer of Record).

At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.