Principal Engineer Design

#WeAreIn to transform theoretical concepts into real hardware designs. Are you in? Your Role Key responsibilities in your new role * As a Low Power Methodology engineer, you will work with the Power Management Architect for feasibility studies. * Drive UPF methodology across frontend and backend teams for power intent and verification. * The person will also be responsible for creating and maintaining workflows for early power estimation, incorporating EDA tools in the Infineon design flow used by all design teams. * Work on low-power design methodology, define methods to derive UPF from higher-level abstractions, and power intent verification methods at the chip level * Work with ASIC design flows and methodologies, including RTL, verification, synthesis, and static timing analysis (STA). * Work with EDA vendors and tools team to define new power methodologies, automated UPF generation, and low power analysis. * Partnering with design and verification teams to troubleshoot and fix UPF-related workflow challenges. * Define and maintain workflows, including EDA tools for early power estimation Your Profile Qualifications and skills to help you succeed * 12+ years of relevant experience * Familiar with low-power design implementation, including UPF/CPF, multi-voltage domains, and power gating. Experience with power intent definition, implementation, and verification flows. * Strong understanding of ASIC design flows and IP design flows. * Very good scripting and programming skills in Python * Good scripting skills in TCL * Familiar with power analysis and optimisation methods. * Hands-on experience with low-power static checkers * Hands-on with Power analysis, estimation and reduction tools like Power Artist, Prime-Power RTL or Joules. * Additional skills in the following areas are a plus: * UPF-based synthesis and implementation * Experience with GitLab, SonarQube, PyTest, VSCode, Git, and Perforce * Familiar with CI/CD pipelines and Software development methods. Familiar with object-oriented programming in Python, Power Software features for power optimisation, Voltage regulators, including Buck and Low Dropout * Power-aware Simulation (RTL/GLS) : Defining chip and macro-level power domains, System Level Power Modelling * Mixed signal power analysis, Power Island/Power Gating/Power Isolation, Structural, Low power design of level shifter and isolation cell topology and associated rules * Architectural analysis and development of digital power optimisation, logic/circuits/SW #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.