Design Verification Engineer - Haifa

## Company: Qualcomm Israel Ltd. ## Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm’s Peripheral IP organization is looking for a Senior Design Verification Engineer to develop the next generation of wired and wireless peripheral subsystems that power Snapdragon® platforms. This is a full‑time, 5 days on site position in Haifa. What You’ll Do * Verify IP and subsystem level peripherals integrated into complex SoCs * Own end‑to‑end verification, including testbench architecture, test planning, execution, and coverage closure * Develop and maintain UVM/SystemVerilog verification environments using constrained‑random testing, assertions, and coverage‑driven methodologies * Collaborate closely with design, architecture, software, and validation teams across multiple sites * Act as a technical focal point for DV methodology, debug, and verification quality Minimum Qualifications * BSc or MSc in Electrical Engineering, Computer Engineering, or a related field * 5+ years of hands‑on design verification experience using SystemVerilog and UVM * Strong understanding of digital design fundamentals and SoC / IP‑level architectures * Proven technical proficiency in: * UVM testbench architecture (agents, sequences, scoreboards, coverage models) * Constrained‑random and coverage‑driven verification * Debugging complex issues in large‑scale regression environments * Scripting and automation using Python, Perl, Tcl, or shell in a Linux/UNIX environment Preferred Qualifications * Motivation and potential to grow into a technical or team‑lead role over time * Experience with high‑speed peripheral IPs such as USB, PCIe, Display, SerDes, or similar I/O subsystems * Knowledge of low‑power design, reset sequencing, and clock‑domain interactions at the IP or SoC level * Familiarity with regression management, verification metrics, and sign‑off criteria * Experience working effectively with global, cross‑site teams What We Offer * Opportunity to verify cutting‑edge peripheral IP used in high‑volume, industry‑leading products * A strong technical environment with opportunities to lead, influence, and mentor * Close collaboration with world‑class design, architecture, CAD, and validation teams * A clear growth path toward senior technical leadership or people management within Qualcomm If you are a technically strong verification engineer with deep UVM expertise and a drive to make real product impact, we’d love to hear from you. To apply: Please submit your CV through the Qualcomm careers portal and reference “Sr DV Engineer – Peripheral IP Group” in your application. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field. *References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies. Qualcomm is an equal opportunity employer. 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