Network Processor IP Verification Sr Lead Engineer

## Company: Qualcomm India Private Limited ## Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job description: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Skills/Experience : 5-8 years of strong experience in digital front end ASIC design verification Bachelors or Masters Degree in Engineering in Electronics, VLSI, Communications or related field. Expertise in RTL verification in C/System Verilog/UVM of complex designs with multiple clock and power domains Being adaptable and have ability to work at various abstraction levels: Block/Core/IP/SS level. Demonstrate strong coding skills in System Verilog and UVM. Develop verification environment and testbench components such as BFMs and checkers. Ability to code Assertion for temporal logic testing. Scripting languages like Perl/Python and development test automation framework for regression automation. Deep understanding of Code/Functional coverage report, identify coverage holes, ability to develop new tests and closing design coverage with design/systems team. Performance verification for throughput/latency analysis of Modem Usecases. Experience in low power verification methodology and clock domain crossing designs Experience of PA GLS verification of DC and PD PG Netlist. Familiarity with various bus protocols like AHB, AXI Experience with Formal Verification is a plus. Experience in Modem/Wireless IP verification on wireless technologies like NR, LTE, WCDMA, CDMA, WLAN, Bluetooth is a plus. Experience in post-Si debug is a plus Good documentation skills Should possess good communication skills to ensure effective interaction with Engineering Management and team members. Should be self-motivated with good teamwork attitude and need to function with minimal guidance or supervision Responsibilities: Digital design verification working in close collaboration with Multi-site Teams across US and India and other Geos. Work in close coordination with Systems, Design, SoC team , SW team, Validation & DFT teams to get the goals completed. Lead junior engineers and drive project planning and tracking. Developing the Verification Strategy, Testbench architecture and implementing the design verification plan and tests using SV/UVM/C. HW verification using Cadence and Synopsys simulator tools, SV/UVM based TB development, Regression analysis, bug-triage. Formal Verification using Jasper, VCF etc. Power Aware Verification on RTL and DC/PD Gate lebel Netlist. Conducting High-/Mid-/Low- level verification reviews, coverage closure and sign-off on block and Sub-system testing. Assisting SOC team with IP Integration testing at SOC level. Post-Silicon Debugs in close collaboration with Design, Validation and SW teams. Self-Motivated to Execute the defined tasks almost independently with minimal guidance Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 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