NPU Design Verification Assoc Engineer

## Company: Qualcomm India Private Limited ## Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Title : NPU Design Verification Engineer Division : Qualcomm Technologies, Inc Job Area : Engineering – Hardware Location : India – Bangalore Education: Bachelors or Master’s degree in EE/CS Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Summary: * Multiple positions for 6-9 years of experience in design verification of complex Qualcomm propriety NPU IP * NPU design team is responsible for delivering high-performance DSP cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space * Qualcomm is the largest fabless design company in the world, generating over $15 Billion in annual revenues from chipsets and royalties from intellectual property. Qualcomm provides hardware, software and related services to nearly every mobile device maker and operator in the global wireless marketplace Job Responsibilities: * Drive design verification of NPU IP by working with a global NPU design team involving architecture, implementation, post silicon and back-end teams * Implement and improve System Verilog Testbench Architecture * Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency * Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals * Hand-on simulations and debug. Work with cross functional Post Silicon teams to debug silicon issues. Provide silicon production quality test content * Complete all required verification activities at IP level and insure high quality commercial success of our products * Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis * Responsible for power aware RTL and gate level simulation Skillset/Experience: * 6-9 years’ experience in processor/ASIC design verification * Solid background and understanding of Digital Design, Processor Architecture and Processor Verification * Expertise in System Verilog Testbench Architecture and implementation * Experience in VERA/System Verilog, simulators from Synopsys/Mentor/Cadence * Scripting/Automation Skills — Perl, Python, Shell, Make file TCI * Solid analytic and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts * Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog and VHDL is preferred * Experience in AMBA, AHB, AXI, JTAG and debug protocols * Gate-Level Simulation and Debug — 0-delay, timing annotated and power aware * Experience is verification of Processor subsystems (ARM/DSP/GPU/NPU) is preferred * Experience in creating validation suite and building automation * Should have excellent inter-personal and communication skills * Exposure to silicon bring up, silicon testing , bench and application testing is a definite plus Applicants: Qualcomm is an equal opportunity employer. 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