sequoiaat~4mo ago

FPGA Emulation Engineer

India·Bangaloremid

OtherEngineer

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Quick Summary

Overview

We are seeking a skilled Hardware Emulation Engineer with hands-on experience in Synopsys HAPS-based prototyping and emulation platforms. The candidate will be responsible for building, debugging, and validating complex SoC and ASIC designs on FPGA-based emulation environments to accelerate…

Key Responsibilities

Develop, integrate, and maintain FPGA-based emulation platforms (Synopsys HAPS, Palladium, or equivalent). Convert RTL designs into emulation-ready models, including partitioning and synthesis for multi-FPGA platforms.

Technical Tools

python

We are seeking a skilled Hardware Emulation Engineer with hands-on experience in Synopsys HAPS-based prototyping and emulation platforms. The candidate will be responsible for building, debugging, and validating complex SoC and ASIC designs on FPGA-based emulation environments to accelerate pre-silicon verification and software validation.

Responsibilities

~1 min read

→Develop, integrate, and maintain FPGA-based emulation platforms (Synopsys HAPS, Palladium, or equivalent).
→Convert RTL designs into emulation-ready models, including partitioning and synthesis for multi-FPGA platforms.
→Perform design bring-up, debug, and hardware/software co-validation using JTAG, logic analyzers, and waveform viewers.
→Collaborate with design, verification, and firmware teams to enable early software execution and system performance analysis.
→Support automation of build flows, configuration management, and regression testing for emulation platforms.
→Analyze timing, resource utilization, and performance metrics to optimize emulation efficiency.
→Document flows, best practices, and debug methodologies for team knowledge sharing.

Requirements

~1 min read

5+ years of experience in FPGA prototyping or hardware emulation of complex SoCs/ASICs.
Hands-on experience with Synopsys HAPS platforms (HAPS-80/100 series preferred).
Strong proficiency in Verilog/SystemVerilog, FPGA synthesis, and place-and-route tools (Synplify Pro, Vivado, or Quartus).
Familiarity with UVM verification, hardware/software co-simulation, and embedded firmware bring-up.
Proficient in debug tools (Identify, Verdi, DVE, or similar).
Scripting knowledge: Tcl, Python, Shell for automation.
Good understanding of SoC architectures, AXI/AHB/PCIe interfaces, and clock/reset domains.