Physical Design Intern

United States·San Joseentry

OtherPhysical Design Engineer

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Quick Summary

Key Responsibilities

Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree synthesis (CTS), and routing.

Requirements Summary

Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Foundational understanding of VLSI design concepts, CMOS circuit design,

Technical Tools

OtherPhysical Design Engineer

About the Role

~1 min read

Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree synthesis (CTS), and routing.
Perform static timing analysis (STA) and work to resolve setup and hold timing violations.
Run and analyze design rule checks (DRC) and layout versus schematic (LVS) checks to ensure design integrity, as well as IR-Drop analysis.
Assist in optimizing power, performance, and area (PPA) metrics using industry-standard EDA tools.
Developing entire P&R/physical verification/IR-EM flows.
Collaborate with front-end design and verification teams to seamlessly integrate RTL changes and resolve physical design constraints.
Help generate and maintain physical design scripts, utilities, and documentation for the team.

Requirements

~1 min read

Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
Familiarity with the basic stages of the ASIC physical design flow.
Academic or project experience with scripting languages such as Python, Perl, or TCL.
Strong analytical and problem-solving skills with a high attention to detail.

Hands-on coursework or project experience with industry-standard EDA tools (e.g., Synopsys ICC2, Cadence Innovus, or similar).
Exposure to Static Timing Analysis (STA) concepts and tools (e.g., PrimeTime, Tempus).
Basic understanding of design constraints (SDC) and library exchange formats (LEF/DEF).
Knowledge of low-power design techniques and power intent formats (UPF/CPF).
Familiarity with AI/LLM tools (e.g., GPT, Copilot) and prompt engineering, with the ability to leverage them to automate EDA scripting, analyze design data, or optimize workflows.