Physical Design Flow Engineer

Tenstorrent is looking for seasoned Physical Design Flow Engineers to develop implementation flows and methodologies for high-performance, low-power designs on advanced technology nodes, with focus on improving Power, Performance, and Area (PPA) in taped-out designs for its next gen products.

This role is hybrid, based out of Santa Clara, CA, Fort Collins, CO or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

• You have a BS/MS in Electrical or Computer Engineering, or equivalent experience, with 5+ years in Physical Design and CAD methodology development.
• You have a strong track record of building implementation flows for high-performance, low-power designs on advanced nodes and delivering measurable PPA improvements in silicon.
• You are hands-on with industry-standard EDA tools such as Fusion Compiler across synthesis, place-and-route, static timing analysis, and signoff closure.
• You are proficient in hierarchical design flows, physical design verification, and scripting in Tcl, Python, or Perl to improve automation, robustness, and efficiency.

• Lead and contribute to cross-functional efforts that solve complex physical design challenges across multiple IPs, projects, and technology nodes.
• Develop and maintain RTL-to-GDS methodologies covering floorplanning, synthesis, place-and-route, static timing analysis, signoff, and chip assembly.
• Optimize EDA tools, flows, and custom CAD solutions to improve PPA, runtime, automation, and overall engineering productivity.
• Partner closely with physical verification, RC extraction, timing, and DFT teams while driving innovative ML-based approaches to design optimization.

• →How advanced AI and high-performance silicon products across multiple IPs and nodes shape physical design methodology choices.
• →How to architect and scale end-to-end RTL-to-GDS flows while balancing PPA, runtime, and schedule in a fast-moving environment.
• →Best practices for integrating implementation, signoff, PV/EMIR, RC extraction, STA, and DFT into a unified, high-yield methodology.
• →How to apply data-driven and ML-based techniques to flow optimization and influence EDA vendor roadmaps based on real production needs.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.