Hardware Intern - AI HW & System on a Chip

Canada·Toronto,Ottawaentry

OtherHardware

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Quick Summary

Key Responsibilities

This posting spans multiple teams within Hardware Architecture & AI Hardware and SoC . One application, one recruiter screen - then we match you to the specific team and location that fits best.

Requirements Summary

We design and develop the core AI accelerator IP, including compute, data movement, and other specialized hardware blocks that enable high-performance AI workloads.

Technical Tools

OtherHardware

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Responsibilities

~2 min read

→Currently pursuing a BS, MS, or PhD in EE, ECE, CE, or CS.
→Coursework or projects in digital design, computer architecture and performance modeling.
→Self-starter who brings sound judgment and practical problem-solving to every project with a solid interest in AI and hardware, along with the ability to take ownership and deliver results.

→Taking designs from specification to RTL to verification, and learning the qualification checks and tools needed to do so.
→How architectural tradeoffs (Architecture: Compute vs. memory vs. interconnect. AI HW/ SOC: Power, Performance & Area) get decided with data, not intuition.
→Best practices for cross-functional collaboration, seeing firsthand how Architecture, RTL, Software, and Physical Design teams stay aligned through implementation.
→Practical methods to integrate AI tools directly into your daily technical workflow.
→[Architecture] Performance modeling methodology used before RTL existed.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Requirements

~1 min read

Familiarity with ASIC design concepts, ranging from performance simulations, RTL design / verification, and logic synthesis / timing analysis
Scripting & programming skills (example: Python, PERL, tcl, C/C++); with experience using AI coding platforms
[Architecture] Experience with architectural simulators.
Exposure to RISC-V or other open ISAs is nice to have.
FPGA design experience is nice to have.