Quick Summary
Overview
Define the HIL bench architecture: real-time target selection, I/O mapping, signal conditioning, safety interlocks,
Technical Tools
Other
- Define the HIL bench architecture: real-time target selection, I/O mapping, signal conditioning, safety interlocks, and fidelity targets
- Develop and validate plant and power-electronics models in OPAL-RT (RT-LAB / HYPERSIM) and MATLAB/Simulink
- Integrate the bench with the client's hardware and software build targets; run closed-loop tests and lead defect triage
- Own the acceptance specification and drive it to sign-off with client engineering
- Direct the offshore controls, test and software engineers: work breakdown, reviews, weekly progress reporting to the client
- Act as custodian for export-controlled technical data; ensure only cleared individuals access controlled material
- 8+ years in controls, test or systems engineering for high-power electronics, plasma, laser, or precision motion systems
- 3+ years hands-on with OPAL-RT (or dSPACE / Speedgoat / NI VeriStand) HIL development
- Strong MATLAB/Simulink, C/C++, real-time systems, and FPGA I/O familiarity
- Experience integrating HIL benches with production firmware and hardware prototypes
- Proven ability to lead distributed teams and communicate with client engineering leadership
- BS/MS in Electrical, Mechatronics or Controls Engineering
Nice to have: semiconductor capital equipment or EUV/DUV source exposure; Python test automation; SECS/GEM or EtherCAT; prior work in ITAR/EAR environment
Location & Eligibility
Where is the job
San Diego, United States
On-site at the office
Who can apply
US
Listing Details
- Posted
- October 11, 2026
- First seen
- October 11, 2026
- Last seen
- October 11, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 54%
- Scored at
- October 11, 2026
Signal breakdown
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