Staff Engineer Design

#WeAreIn to leverage synergies contributing to Infineon’s product development.​ Are you in? Your Role Key responsibilities in your new role * Develop and implement high-performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools. * Work closely with design teams to understand the requirements and constraints of the design, and provide feedback on design feasibility,timing and power. * Write and implement block level and top-level constraints for synthesis, perform timing closure and power analysis. * Develop and implement synthesis flows and methodologies, and driveimprovements in the design process. * Debug and resolve design issues related to synthesis, timing, power, and area. * Understanding of DFT flows, including scan insertion and ATPG. * Optimize designs for power,performance, and area, and meet design goals within the given schedule. * Implement pipelining at different levels for performance optimization and timing closure. * Perform power analysis and optimize designs for lowpower. * Have experience in mentoring junior engineers. * Proficient with EDA tools from Synopsys/Cadence/Mentor. * Excellent analytical & communication skills. Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone. * Proficient in Tcl and Perl or other scripting relevant language is a plus Your Profile Qualifications and skills to help you succeed * B.Tech/M.Tech in Electronics or related domains. * 4+ years of relevant experience. * Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations. * Candidate should have strong Synthesis/STA fundamentals. * Has done timing sign-off including timing margin calculations independently, hands-on STA lead of projects. * Experience in handling STA of multi-power domain designs & constraint mode merging. * STA flow development, abstraction with bottleneck identification. • Proficient in design margins and SDC constructs. * TAT reduction in multi-mode, multi power domain/designs. * Generate timing ECOs for Physical design. * Drive ambitious schedules and enables dependent teams to accomplish. * Interface to design team and PD team and drive TAT reduction for PD(Physical Design). * Has experience in mentoring junior engineers. * Proficient with EDA tools from Synopsys/Cadence. * Excellent analytical & communication skills. * Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone. * Proficient in Tcl and Perl or other scripting relevant language is a plus. Contact: Gowri Shenoy, LinkedIn #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.