SMTS, Design Rule Enablement Team TPG

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

• →Lead efforts to develop and refine Design Rules, Requirements, and Test Structures for all DRAM generations and associated advanced CMOS.
• →Define milestones for projects within the layout schedule and work with the various teams to achieve the targets and time-lines Partner with Design, Product Engineering, Process integration, Business Units and Quality groups to optimize PPAC (Performance, Power, Area, Cost) for all Micron DRAM products 
• →Manage test structure evaluation to support next-gen device development and quantify process margins.
• →Define sub-milestones within layout schedules and ensure timely execution across teams.
• →Address process window vs. die size issues arising from database layout techniques.
• →Collaborate with Design, Product Engineering, Process Integration, Business Units, and Quality teams to optimize PPAC (Performance, Power, Area, Cost).
• →Ensure robust Design Rule Checks (DRC) and appropriate responses to deviations.
• →Strategically partner with multiple teams and fields to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design 
• →Document and communicate complex problem resolutions and drive cross-node design rule alignment.
• →Maintain effective communication across Process Integration, Product Engineering, Design, and Advanced Mask teams.
• →Improve documentation of R&D activities for design rule improvement
• →Ability to define and implement design rules within APR workflows to enhance layout efficiency and manufacturability.
• →Ability to utilize AI framework and develop workflow compatible with LLMs & other GenAI techniques for efficiency gain

• MS/PhD in Electrical Engineering, Microelectronics, Physics, or related field.
• 15+ years of experience in semiconductor industry in areas such as Process Integration, PDK development, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process Development.
• Strong understanding of semiconductor process flow and key components of DRAM & advanced CMPS (e.g., Sense Amp, Word-line driver, Anti-Fuse, GAA, FinFET etc.).
• Experience with Test Structure Design and Characterization.
• Familiarity with Cadence & Siemens tools and ability to perform layout tasks.
• Proven success in resolving complex technical issues and communicating clearly under pressure.
• Exposure to CAD group interactions, data post-processing, and database/reticle data transfer.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

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